The present invention relates to a nonvolatile memory which has a density of integration and a low operating voltage.
In general, nonvolatile memories used as EEPROMs (Electrically Erasable and Programmable ROMs) or EAROMs (Electrically Alterable ROMs) are constructed of MISFETs (Metal-Insulator-Semiconductor Field Effect Transistors) which are broadly classified into two types; the FLOTOX (Floating Tunnel Oxide) type belonging to the floating gate type, and the MNOS (Metal-Nitride-Oxide-Semiconductor) type. The former has a control gate electrode for control, and a floating gate electrode for storing a charge. The charge carriers to be stored in the floating gate are injected thereinto by passing them through a thin oxide film (e.g. 2 nm-20 nm on a drain region owing to the modified Fowler-Nordheim tunneling (MFN tunneling) or the direct tunneling (hereinbelow, simply termed "tunneling"). On the other hand, the latter has its gate insulator film formed of a double-layer structure consisting of a silicon dioxide film (SiO.sub.2 film) and a silicon nitride film (Si.sub.3 N.sub.4 film) deposited thereon. Charge carriers are tunneled through the SiO.sub.2 film, thereby to be injected and stored in those traps within the Si.sub.3 N.sub.4 film which are formed near the boundary of the two insulator films.
The respective semiconductor devices, however, have certain problems, to be discussed below, which serve to hamper enhanced densities of integration and lowered operating voltages of the memories.
The FLOTOX is particularly advantageous in data retention. In order to ensure the retention of the charges, however, a thick inter-layer insulator film of about 1000 .ANG., similar to that used in a conventional EPROM (Erasable and Programmable ROM), needs to be interposed between the floating gate and the control gate. The thickness is required for preventing the stored charge of the floating gate from leaking to the control gate. It is therefore impossible to simply apply scaling-down procedures for the purpose of enhancing the density of integration. Besides, in the FLOTOX, in constructing memory cells, the registration between the drain regions previously formed and the floating gates becomes a serious problem. Since an allowance for alignment is required, the fine processing of a pattern attendant upon an enhanced density of integration becomes very difficult.
With the MNOS, the alignment between gates and drain regions is not a problem. In addition, the latter is advantageous in endurance. However, scaling-down the device for the purpose of enhancing the density of integration cannot be simply performed on the MNOS, either. When the Si.sub.3 N.sub.4 film constituting the gate insulator film becomes thinner than a certain value (generally about 200 .ANG.) by reason of the scaling-down procedure, there arises the phenomenon that the charge carriers are emitted to a gate electrode. Therefore, retention becomes a serious problem. In this manner, the reduction of the thickness of the Si.sub.3 N.sub.4 film, namely, the scaling-down is limited, which forms obstacles to enhancing the density of integration and lowering the operating voltage.